A charge redistribution type DAC has a plurality of capacitors which are coupled to one another in parallel. The plurality of capacitors have capacitance values which are weighted by a binary rate (1:2:4:8: . . . :2L). In the following description, “DAC” means the charge redistribution type DAC. Under a reset state, the charge states of the plurality of capacitors in DAC are reset while the common coupling node of the plurality of capacitors is set to a reference potential. On the other hand, under an operation state, any one of a high reference voltage and a low reference voltage is applied to electrodes of the plurality of capacitors at the opposite side to the common coupling node, out of the electrodes of the plurality of capacitors, to generate an analog output voltage at the common coupling node.
The DAC is disclosed in patent documents, for example, Japanese Laid-open Patent Publications No. S-57-124933, No. S-62-245723, No. 2002-190732, No. 2001-160757 and No. H-2-155457 and in a non-patent document, for example, Kul B. Ohri, Michael J. Callahan Jr.; Integrated PCM codec, IEEE Journal of Solid-State Circuits, vol. 14, pp. 38-46, February 1979.
With respect to the DAC, the number of capacitors increases as the number of bits of a digital input signal increases. When the number of capacitors increases, the capacitance values of capacitors corresponding to upper-side bits (MSB-side bits) are larger. The increase of the capacitance values of the capacitors causes an increase of the chip area of an integrated circuit. Therefore, there has been proposed a DAC having a coupling capacitor provided between a capacitor group of capacitors corresponding to upper-side (MSB-side) bits and a capacitor group of capacitors corresponding to lower-side (LSB-side) bits. In the DAC having the coupling capacitor, the capacitance values of the capacitor groups at the upper side and at the lower side are respectively weighted by binary rates. The DAC having the coupling capacitor is disclosed in the above patent documents and the above non-patent document.
Furthermore, a successive approximation analog digital converter (ADC) having the DAC samples an analog input voltage and compares the sampled analog input voltage with a comparison target voltage generated by the DAC. This comparison operation is successively repeated from the most significant bit (MSB) of the digital input signal of the DAC to the least significant bit (LSB). In the successive approximation operation, a comparison target voltage in the approximation operation for a lower-side bit is varied in accordance with a comparison result of an upper-side bit which is just above the concerned lower-side bit.
The successive approximation ADC is disclosed in non-patent documents, for example, Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes; A 0.5V, 1 μW successive approximation ADC, Proceedings of the 28th European Solid-State Circuits Conference, September 2002, and Hae-Sung Lee, David A. Hodges, Paul R. Gray; A self calibrating 12 b 12 μs CMOS ADC, IEEE International Solid-State Circuits Conference, vol. XXVII, pp. 64-65, February 1984. The successive approximation ADC has a DAC for generating a discrete comparison target voltage. The ADCs described in the non-patent documents have analog input terminals, a DAC, a comparator for comparing an analog input voltage and a comparison target voltage, and a Successive Approximation Register Logic Circuit (SAR logic circuit) for storing the results of the comparator to output a digital output signal. The digital input signal of the DAC is generated in accordance with the comparison result at each bit by the SAR logic circuit.
In the DAC having the coupling capacitor provided between the upper-side and lower-side capacitor groups, it is required to form the capacitance value of the coupling capacitor with high precision. The patent documents propose a circuit construction in which the capacitance value of the coupling capacitor is equal to the capacitance value of the capacitor of the least significant bit.